Verilog_intro (2)

[Audio] California State University at Sacramento ENGINEERING - ELECTRICAL AND ELECTRONIC CpE/EEE 64 – Introduction to Logic Design Verilog HDL.

Introduction to Hardware Description Language (HDL).

What is HDL? • It is a specialized computer language • Used to describe the structure and behavior of electronic circuits • HDLs include the notion of time • HDLs support Concurrency.

Verilog • Verilog is a Hardware Descriptive Language (HDL) standardized as IEEE 1364-2001 • Verilog is used to describe the low level hardware • Syntax is similar to that of C-Language.

Verilog A Hardware Description Language(HDL) used to model electronic system HDLs have a notion of time Helps to design and describe digital system Files have .v file extension A general purpose programming language that allows structured programming Do not have notion of time Helps to build operating systems, databases, compilers, interpreters etc. Files have .c file extension.

VHDL • VHDL stands for VHSIC (very high speed integrated circuit) Hardware Descriptive Language • It can model the behavior and structure of digital system at multiple abstraction levels • VHDL is strongly typed and very deterministic.

Verilog versus VHDL Verilog Used to model electronic system Verilog is weakly typed Based on C language Case sensitive Simple data types Verilog is newer that VHDL Less complex VHDL Used in electronic design automation to describe digital and mixed signal system VHDL is strongly typed Based on Pascal and Ada language Not Case sensitive More complex data types Older than Verilog More complex.

Verilog Level of abstraction.

Objective • Switch Level • Gate Level • Data Flow Level • Behavioral Level.

Switch Level • At this level a module can be implemented in terms of switches • Here nmos and pmos are used as switches for the design.

Syntax: mos_name instance_name (output, data , control) Example: module inverter(Q,A); input A; output Q; supplyl vdd; suppltO vss; pmos p (Q,vdd,A); nmos n (Q,vss,A); endmodule Vdd Vss.

Gate Level • At this level module is implemented in terms of logic gates • Gate Level is the lowest level of abstraction • Basic logic gates are available as predefined primitives.

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Data Flow Level • Register Transfer Level • At this level, module is designed by specifying the data flow • signals are assigned by the data manipulating equations • Design is implemented using continuous assignments All such assignments are concurrent in nature.

• "assign" keyword is used Example: assign z = x & y; assign p = q I r; assign z ;.

Behavioral Level • This is the highest level of abstraction provided by HDL • Behavioral level describes the system by its behavior • Different elements like function, task, and blocks can be used • Two important constructs under this level are initial and always.

Example: (2* 1 mux) always@(iO,i1,sel) begin if(sel) out else out = iO; end.

Modules and Instantiation.

Modules • A module is the basic building block in Verilog. • A module can be an element or a collection of lower- level design blocks. • It provides the required functionality to the higher- level block through its port interface but hides the internal implementation. • It provides the flexibility to the designer to modify the module internals without affecting the rest of the design..

Verilog Framework: module module _ name (x,y,z); input x,y; output z; statements ; endmodule.

Module Instantiation • Instantiation allows the creation of hierarchy in Verilog description. • It is a process of creating object from a module template and the objects are called instances. • In Verilog, nesting of module is illegal. • One module definition cannot contain another module definition. • we can incorporate the copies of other module by instantiating them..

Example: 4* 1 mux using 2*1 mux module mux_2t01 (iO,i1,sel,out); input iO,i1,sel; output out; always@(iO,i1,sel) begin if(sel) out else out = iO; end endmodule 10 out.

module mux_4t01 (iO,i1,i2,i3,s1,sO,out); input iO,i1,i2,i3,s1,sO; output out; wire xl,x2; mux_2t01 ml (iO,i1,s1,x1); mux_2t01 m2 (i2,i3,s1,x2); mux_2t01 m3 (xl,x2,sO,out); endmodule.

Verilog Keywords • Case sensitive • $, underscore, alphanumeric characters can be used Example: • new block • new blockl • new_block$ • Inew block • $new_block • 1 new block.

Comments Comments are basically used for documentation. It also improves the readability of the code. There are two ways to write the comment: • Single-line comment- It starts with "//". Verilog skips from that point to the end of the line. • Multiple-line comment- It starts with "/*" and ends with "*/" Multiple-line comment cannot be nested..

Example: assign z = x y; /) z is equal to assign r = p & q; / * This is multiline comment * /.

[Audio] ModelingStructure:Ports �ModulePorts Similartopinsonachip Provideawaytocommunicatewithoutsideworld Portscanbeinput,outputorinoutModuleAND(i0,i1,o);inputi0,i1;outputo;i0oi1endmodule.

[Audio] Verilog Primitives � Basic logic gates only and or not buf xor nand nor xnor bufif1, bufif0 notif1, notif0.

[Audio] Primitive Pins Are Expandable � One output and variable number of inputs nand (y, in1, in2) ; nand (y, in1, in2, in3) ; nand (y, in1, in2, in3, in4) ; � not and buf variable number of outputs but only one input.

[Audio] Continuous Assignments � Describe combinational logic � Operands + operators � Drive values to a net assign out = a&b ; // and gate assign eq = (a==b) ; // comparator wire #10 inv = ~in ; // inverter with delay wire [7:0] c = a+b ; // 8-bit adder � Avoid logic loops assign a = b + a ; asynchronous design.

[Audio] Logical and Conditional Operators � Logical, bit-wise and unary operators a = 1011; b = 0010 logical bit-wise unary a || b = 1 a | b = 1011 |a = 1 a && b = 1 a &b = 0010 &a = 0 � Conditional operator assign z = ( == 2'b00) ? IA : ( == 2'b01) ? IB : ( == 2'b10) ? IC : ( == 2'b11) ? ID : 1'bx ; assign s = (op == ADD) ? a+b : a-b ;.

[Audio] Operators +, -, *, /, % Arithmetic Operators <, <=, >, >= Relational Operators ==, !=, ===, !== Equality Operators !, &&, || Logical Operators ~, &, |, ^, ~^ Bit-Wise Operators &, ~&, |, ~|, ^, ~^ Unary Reduction >>, << Shift Operators ?: Conditional Operators {} Concatenations.

[Audio] Operator Precedence [ ] bit-select or partselect >, >=, <, <= relational ( ) parentheses ==, != logical equality & bit-wise AND !, ~ logical and bit-wise negation &, |, ~&, ~|, ^, ~^, ^~ ^, ^~, ~^ bit-wise XOR and XNOR reduction operators | bit-wise OR +, - unary arithmetic && logical AND concatenation || logical OR ? : conditional *, /, % arithmetic +, - arithmetic <<, >> shift.

[Audio] Operators ~ bit-wise NOT concatenation & bit-wise AND | bit-wise OR + - * / arithmetic ^ bit-wise XOR % modulus ^~ ~^ bit-wise XNOR & reduction AND > >= < <= relational | reduction OR ! logical NOT ~& reduction NAND && logical AND ~| reduction NOR || logical OR ^ reduction XOR == logical equality != logical inequality ~^ ^~ reduction XNOR <> shift right ? : conditional.

[Audio] Example � 4-bit adder module add4 (s,c3,ci,a,b) input [3:0] a,b ; // port declarations input ci ; output [3:0] s : // vector output c3 ; wire [2:0] co ; add a0 (co[0], s[0], a[0], b[0], ci) ; add a1 (co[1], s[1], a[1], b[1], co[0]) ; add a2 (co[2], s[2], a[2], b[2], co[1]) ; add a3 (c3, s[3], a[3], b[3], co[2]) ; endmodule a0 a1 a2 a3 c3 ci.

[Audio] Sample Design module fadder ( sum, cout, a, b , ci ); 1-bit full adder // port declaration sum output sum, cout; input a, b, ci; a b ci reg sum, cout; // behavior description cout always @( a or b or ci ) begin sum = a ^ b ^ ci; cout = ( a&b ) | ( b&ci ) | ( ci&a); end endmodule.

[Audio] A full-adder � module Circuit (co, s, a, b, c) input a, b ,c ; output co, s ; xor (n1, a, b) ; xor (s, n1, c) ; nand (n2, a, b) ; nand (n3,n1, c) ; nand (co, n3,n2) ; endmodule.

[Audio] Numbers Format : ' Example : 8'd16 8'h10 8'b00010000 8'o20.

[Audio] Keywords Note : All keywords are defined in lower case Examples : module, endmodule input, output, inout reg, integer, real, time not, and, nand, or, nor, xor parameter begin, end fork, join specify, endspecify.

[Audio] Value Set in Verilog 4-value logic system in Verilog : '0' 'X' '1' 'Z' 0.

[Audio] Major Data Type Class ØNets ØRegisters ØParameters.

[Audio] Nets ØNet data type represent physical connections between structural entities. ØA net must be driven by a driver, such as a gate or a continuous assignment. ØVerilog automatically propagates new values onto a net when the drivers change value..

[Audio] Registers & Parameters ØRegisters represent storage elements. ØA register holds its value until a new value is assigned to it. ØRegisters are used extensively in behavior modeling and in applying stimuli. ØParameters are not variables, they are constants..

[Audio] Assignments Assignment : drive values into nets and registers. Continuous Assignments – Any changes in the RHS of continuous assignment are evaluated and the LHS is update. Example : (1) assign out = ~in; (2) assign reg_out; = reg_in << shift.

[Audio] Assignments ( cont. ) Blocking procedural assignment. rega = regb + regc; Non-blocking procedural assignment. rega <= regb * regc;.

[Audio] Sequential Circuit Design. Sequential Circuit Design.

[Audio] Sequential Circuit Design Inputs Outputs Combinational circuit Memory elements – a feedback path – the state of the sequential circuits – the state transition G synchronous circuits G asynchronous circuits.

[Audio] Finite State Machine � Moore model outputs current state inputs memory elements comb. circuit next state comb. circuit � Mealy model outputs current state inputs memory elements comb. circuit next state comb. circuit.

[Audio] Examples D flip-flop D latch register shifter counter pipeline FSM.

[Audio] Flip-Flop � Synchronous clear module d_ff (q,d,clk,clr_) ; output q ; input d,clk,clr_ ; reg q ; always @ (posedge clk) if (~clr_) q = 0 ; else q = d ; endmodule � Asynchronous clear always @ (posedge clk or negedge clr_) if (~clr_) q = 0 ; else q = d ;.