Name: UNIT - 1
Uploaded: 2022-04-19
Duration: 6 min 14 s
Description: UNIT - 1. Synchronous sequential Logic Circuit- State Transition Diagram-state Machine-State Minimization in Sequential Logic Equivalent State-Cellular Sequential Logic..

UNIT - 1. Synchronous sequential Logic Circuit- State Transition Diagram-state Machine-State Minimization in Sequential Logic Equivalent State-Cellular Sequential Logic.. 

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Synchronous sequential Logic Circuit- State Transition Diagram-state Machine-State Minimization in Sequential Logic Equivalent State-Cellular Sequential Logic.

SR (or RS) flip-nop It is also called Set/Reset flip-flop. The logic symbol Of SR flip-flop is shown in figure: Set s Reset SR Normal Complementary Figure : Symbol of SR flip-flop The SR flip-flop has two inputs and two outputs. The inputs are S (Set) and R (Reset). The outputs Q and Q are complements to each other. i.e. when Q = O, Q will be 1 and when Q = l, Will be O. The logic diagram Of SR flip-flop using NANI) gates and the truth table are shown in figure. s 3 4 2. 

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SR (or RS) flip-nop
It is also called Set/Reset flip-flop. The logic symbol Of SR flip-flop is shown in
figure:
Set
s
Reset
SR
Normal
Complementary
Figure : Symbol of SR flip-flop
The SR flip-flop has two inputs and two outputs. The inputs are S (Set) and R (Reset).
The outputs Q and Q are complements to each other. i.e. when Q = O, Q will be 1 and when Q
= l, Will be O. The logic diagram Of SR flip-flop using NANI) gates and the truth table are
shown in figure.
s
3
4
2

Lo ic dia ram of SR fli -flo s o o 1 Inputs R 0 1 o 1 Outputs Q Previous Previous value 0 1 value 1 0 Condition No change Reset Set Not used Forbidden Figure : Truth table of SR flip-flop. 

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Lo ic dia ram of SR fli -flo
s
o
o
1
Inputs
R
0
1
o
1
Outputs
Q
Previous Previous
value
0
1
value
1
0
Condition
No change
Reset
Set
Not used
Forbidden
Figure : Truth table of SR flip-flop

Clocked SR (CSR) flip-flop. s 3 -J¯LcLK 4 2 Figure : Logic circuit of CSR flip-flop Inputs CLK S R Outputs Q Previous Previous value value Forbidden Condition NO Change Reset Not used Figure : Truth table of CSR flip-flop. 

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s
3
-J¯LcLK
4
2
Figure : Logic circuit of CSR flip-flop
Inputs
CLK S
R
Outputs
Q
Previous Previous
value
value
Forbidden
Condition
NO Change
Reset
Not used
Figure : Truth table of CSR flip-flop

Set
Reset
CSR
Complementary
Figure : Logic symbol of CSR FF

Normally, sequential logic circuits work in sequence with on the occurrence of clock signal. Clock signal is a train of pulses in the form of square wave. Clocked SR flip-flop is similar to SR flip-flop with an additional clock input. The output of the FF changes only on the arrival of the clock signal.

JK Flip-flop The NOT USED condition of SRFF i.e. S=l, R=l condition is eliminated in the JK flip-flop. The condition J=l, K=l is used to toggle the flip-flop. Toggling means, when the previous output is '0', the present output will be 'l'. Similarly, when the previous output is 'l ', the present output will be'0'. JK FF has three inputs J, K and CLK and two outputs Q and Q. Preset (Pr) and Clear (Cr) inputs are also provided in the JK FF. The logic symbol, logic circuit diagram and truth table of JK FF are shown in figure. Clk JK Figure : Logic symbol Of JK FF. 

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JK Flip-flop
The NOT USED condition of SRFF i.e. S=l, R=l condition is eliminated in the JK
flip-flop. The condition J=l, K=l is used to toggle the flip-flop. Toggling means, when the
previous output is '0', the present output will be 'l'. Similarly, when the previous output is
'l ', the present output will be'0'.
JK FF has three inputs J, K and CLK and two outputs Q and Q. Preset (Pr) and Clear
(Cr) inputs are also provided in the JK FF. The logic symbol, logic circuit diagram and truth
table of JK FF are shown in figure.
Clk
JK
Figure : Logic symbol Of JK FF

2 pr 3 4 Cr Figure : Logic circuit diagram of JK FF In uts CLK J K Out uts Previous value Previous value Condition NO change Set Toggle Complement Complement of Previous of Previous value value Figure : Truth table of JK FF. 

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2
pr
3
4
Cr
Figure : Logic circuit diagram of JK FF
In uts
CLK J K
Out uts
Previous
value
Previous
value
Condition
NO change
Set
Toggle
Complement Complement
of Previous of Previous
value
value
Figure : Truth table of JK FF

Master Slave ( KMS) flip-flOP The racing problem in JK FF can avoided by using JKMS FF. The logic symbol Of JKMS FF is show in figure. JKMS Clk Figure : Logic symbol of JKMS FF In JKMS FF there are two JkFFs, one Master JKFF and one Slave JKFF. CLK pulse Of the master section is inverted and then given to the CLK input of the slave section. Clk Master JK Slave JK Cr Figure : JKMS FF using two JK FF The logic circuit diagram and truth table Of JKMS FF are shown in figure.. 

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Master Slave (
KMS) flip-flOP
The racing problem in JK FF can avoided by using JKMS FF. The logic symbol Of
JKMS FF is show in figure.
JKMS
Clk
Figure : Logic symbol of JKMS FF
In JKMS FF there are two JkFFs, one Master JKFF and one Slave JKFF. CLK
pulse Of the master section is inverted and then given to the CLK input of the slave section.
Clk
Master
JK
Slave
JK
Cr
Figure : JKMS FF using two JK FF
The logic circuit diagram and truth table Of JKMS FF are shown in figure.

CLK Master 3 4 Slave 5 6 2 Figure : Logic Circuit diagram Of JKMS FF In uts J o Out uts CLK K o Previous value Previous value Complement Complement of Previous of Previous 7 8 Condition No change Set Toggle value value Figure : Truth table of JKMS FF NAND gates l, 2, 3 and 4 form the Master section and NAND gates 5, 6, 7 and 8 form the slave section. NOT gate is used to generate the inverted clock for the slave section.. 

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CLK
Master
3
4
Slave
5
6
2
Figure : Logic Circuit diagram Of JKMS FF
In uts
J
o
Out uts
CLK
K
o
Previous
value
Previous
value
Complement Complement
of Previous of Previous
7
8
Condition
No change
Set
Toggle
value
value
Figure : Truth table of JKMS FF
NAND gates l, 2, 3 and 4 form the Master section and NAND gates 5, 6, 7 and 8
form the slave section. NOT gate is used to generate the inverted clock for the slave section.

3.1.5 T Flip-nop The T (Toggle) Flip-flop is formed by connecting the J and K inputs of JKMS FF together. (or) In a JKMS FF, when we make J = K, we will get a T FF. This is shown in figure. Clk JKMS Cr Figure : Logic diagram of T FF The truth table of T FF is shown in figure. In uts Ou uts Previous value Previous value Condition NO change Toggle Complement Complement of Previous of Previous value value Figure : Truth table of T FF. 

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3.1.5 T Flip-nop
The T (Toggle) Flip-flop is formed by connecting the J and K inputs of JKMS FF
together. (or) In a JKMS FF, when we make J = K, we will get a T FF. This is shown in
figure.
Clk
JKMS
Cr
Figure : Logic diagram of T FF
The truth table of T FF is shown in figure.
In uts
Ou uts
Previous
value
Previous
value
Condition
NO change
Toggle
Complement Complement
of Previous of Previous
value
value
Figure : Truth table of T FF

D Flip-flop. Inputs CLK D JKMS cr Figure : Logic diagram Of D FF Outputs Condition Reset Figure : Truth table off) FF. 

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Inputs
CLK D
JKMS
cr
Figure : Logic diagram Of D FF
Outputs
Condition
Reset
Figure : Truth table off) FF

State Transition Diagram. A state transition diagram is a graphical representation o It consists of nodes, representing the internal states , and flow lines between nodes, which are labelIed with the inputs causing the state transition and the resulting output. The state transition diagram for the JKFF‘ is given in Fig . There are two nodes qo and q, representing the internal states 0 and 1 . The flow lines are labelIed JK/Q where J and Kare the inputs and Q is the output.. 

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A state  transition diagram is a  graphical representation o It consists of nodes, representing the  internal states , and flow lines between nodes, which are  labelIed  with the inputs causing  the state  transition and the resulting  output. The state transition diagram for the  JKFF‘ is  given in Fig . There are two nodes  qo  and q, representing the internal states 0 and 1 . The flow lines are  labelIed  JK/Q where J and  Kare  the inputs and Q is the output.

A state transition diagram for a JKFF. 10/1 11/1 01/0 00/0 01/0 11/0 10/1. 

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A state transition diagram for a JKFF.
10/1
11/1
01/0
00/0
01/0
11/0
10/1

Next state
Input JK
01
11
10
Pregnt state

pqttern or Sequence Detector (Example) in a string of bits Design a segnce detector to detect ee more c through m Input Ime 0 000 t (MM). 

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pqttern or Sequence Detector (Example)
in a string of bits
Design a segnce detector to detect ee more c
through m Input Ime
0 000 t (MM)

PROBLEM. Design a sequential logic circuit that will detect the sequence 101 in a stream of serial data, input at the rate of 1 bit per clock pulse. The circuit has a single input variable I which is either 0 or 1, and a single output Z that becomes 1 when the input sequence 101 has been received. However, it is not obvious at the outset how many internal states are required. The internal states are identifiable from a state transition diagram. Let internal state A be the initial state where none of the input bits have arrived in the correct sequence. In state A, the external input can be either 0 or 1. If I = 0 we remain in state A as. 

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Design a  sequential logic  circuit that will detect the sequence 101 in a stream of serial data, input at the rate of 1 bit per clock pulse. The circuit has a single input variable I which is either 0 or 1, and a single output Z that becomes 1 when the input sequence 101 has been received. However, it is not obvious at the outset how many internal states are required. The internal states are identifiable from a state transition diagram. Let internal state A be the initial state where none of the input bits have arrived in the correct sequence. In state A, the external input can be either 0 or 1. If I = 0 we remain in state A as

the input does not correspond with the first bit in the sequence we wish to detect. If, however, I = 1 the first bit in the sequence has occurred. This condition is represented by new internal state B. The output in both cases is zero as the complete sequence has not yet been detected. When in state B further input data can be received. If I = 0 the second bit of the sequence 101 has arrived and we switch to state C. If I = 1 the current input might still be the first bit of the sequence 101 and the system should remain in B. The complete state transition diagram is given in fig. 

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the input does not correspond with the first bit in the sequence we wish to detect. If, however, I = 1 the first bit in the sequence has occurred. This condition is represented by new internal state B. The output in both cases is zero as the complete sequence has not yet been detected. When in state B further input data can be received. If I = 0 the second bit of the sequence 101 has arrived and we switch to state C. If I = 1 the current input might still be the first bit of the sequence 101 and the system should remain in B. The complete state transition diagram is given  in fig

The present/nextstate table is: Next state B Present state C D A c A A B D B. 

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The present/nextstate table is:
Next state
B
Present
state
C
D
A
c
A
A
B
D
B

Assigning binary values to the internal states (let A B -01, Cz 11 and D = 10)

10
01
10
10
11
00
0-1
11
00 to
10
axaN

State Minimization in Sequential Logic. Next state Pregnt state Output Z Input I Input I B c 1/0 Fig. 5.13 A minimized state transition diagram and tables for the 101 sequence detector.. 

Scene 17

Next state
Pregnt
state
Output Z
Input I
Input I
B
c
1/0
Fig. 5.13
A minimized state transition diagram and tables for the 101 sequence
detector.

problem. Design a sequential system, using 2 JKFFs and driving logic, that detects the pattern 1011 in a stream of bit-serial data.. 

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Design a sequential system, using 2 JKFFs and driving logic, that detects the pattern 1011  in a  stream of bit-serial data.

State Reduction and Assignment State Reduction and Assignment 016 010 b: 00 L C : OLO Loo. 

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State Reduction and Assignment
State Reduction and Assignment
016
010
b: 00 L
C : OLO
Loo

State Reduction and Assignment State Reduction and Assignment 016 0/0 b: 00 L e— Loo. 

Scene 20

State Reduction and Assignment
State Reduction and Assignment
016
0/0
b: 00 L
e— Loo

Ito,p 010: 00 0/0 puo uogonpau IU9WU5!SSV pue uogonpau. 

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Ito,p
010:
00
0/0
puo uogonpau
IU9WU5!SSV pue uogonpau

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PROBLEM EQUIVALENT STATE MINIMIZATION USING IMPLICATION CHART. 

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PROBLEM  EQUIVALENT STATE MINIMIZATION USING IMPLICATION CHART

Present state Next State, Next State, Present Output. 

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Present state
Next State, Next State,
Present Output

Scene 25

. Present state Next State, X-O Next State, X-I Present Output. 

Scene 26

Present state
Next State, X-O
Next State, X-I
Present Output