RF_Input

[Audio] Hello, we present a low-cost spectrum analyzer design based on an open and extensible architecture for RF analysis..

[Audio] Radio Frequency also known as RF signals are electromagnetic waves that oscillates at a high frequency, ranging from 3 kHz to 300 GHz. A spectrum analyzer enables visualization of signal strength across frequency, revealing information that time-domain tools like oscilloscopes cannot provide..

[Audio] Our system supports three core applications. They are, real-time signal visualization of RF signals up to 3.2GHz, interference detection, and RF system debugging..

[Audio] project has three main objectives. First, to develop a low-cost architecture using off-the-shelf components. Second, to build an interactive and user-friendly interface on standard processing platforms. And finally, to establish a research foundation that bridges low-cost solutions with high-end industrial RF tools..

[Audio] Further, project consists of three main deliverables. First, the RF front-end, where we redesigned and implement the complete RF signal path. Second, the DSP firmware on the Zed Board, where advanced digital signal processing algorithms were implemented. Finally, the UI and validation stage focused on developing an interactive user interface and validating system performance through in-lab testing. We will now explain each component in detail..

[Audio] Now let's move on to the overall Architectural block diagram of the system..

[Audio] We begin our architecture design with the foundational element of any receiver system: the RF Input. This represents our raw, incoming radio frequency signal before any processing or conditioning takes place..

[Audio] The very first block the signal encounters from the RF input is the Coupler. The coupler allows us to sample a fraction of the input signal power without significantly disrupting the main signal path..

[Audio] As we look at the coupler outputs, we see two distinct paths emerging: the main through-path continuing forward to the right, and a coupled sample path diverted downward..

[Audio] To safeguard our system and monitor signal levels, the down-sampled path from the coupler is routed directly into a Power Detector. This gives us real-time visibility into the exact power level of the incoming RF signal..

[Audio] The power detector converts the RF power reading into a corresponding analog voltage, which is then fed into a Microcontroller Unit, or MCU. This MCU acts as the brain for our initial hardware protection layer..

[Audio] The MCU uses that power reading to drive a Digital Step Attenuator (DSA) placed right in the main signal path. Together, the Coupler, Power Detector, MCU, and DSA form a closed loop known as the Input Power Handling Stage, ensuring our system is never overloaded by excessively hot signals..

[Audio] Once the signal passes through the attenuation stage safely, it enters a 3.2 GHz Low-Pass Filter (LPF). This filter acts as a crucial gatekeeper, cleaning up any out-of-band high-frequency noise or interference..

[Audio] Following the low-pass filter, we introduce a Control Switch. This component gives our architecture flexibility, allowing us to route the signal down different processing paths depending on system requirements..

[Audio] The upper path of this switch routes the signal into a Pre-Amp (Preamplifier) to boost weak signals and optimize our overall system noise figure..

[Audio] By terminating that switch into a bypassable network, we create a distinct Pre-Amplification Stage. We can now explicitly choose whether to amplify the filtered signal or pass it straight through if the input power is already sufficient..

RF_Input. Coupler. PD. MCU. DSA. 3.2GHz LPF. Pre Amp.

[Audio] To bring our high-frequency RF signal down to a manageable level, we pass it into our first mixer, M1, to produce the first Intermediate Frequency, IF1. This mixer is driven by VCO1, a programmable Voltage-Controlled Oscillator operating across a 5 to 8.2 GHz band..

[Audio] o achieve better selectivity and filtering, we down-convert a second time. The IF1 signal is fed into a second mixer, M2, resulting in IF2. This stage uses a static VCO2 locked at 4.688 GHz..

[Audio] Our architecture utilizes a triple-conversion design. The signal is down-converted one final time through a third mixer, M3, yielding IF3. This mixer is driven by a static VCO3 tuned to 307 MHz, rounding out our comprehensive Mixing Stage..

[Audio] Now that the signal has been down-converted to a clean, low-frequency IF, it leaves the analog domain entirely by entering an Analog-to-Digital Converter (ADC), turning the physical wave into digital data..

[Audio] The digitized stream from the ADC is routed directly into an FPGA (Field Programmable Gate Array). The FPGA handles the heavy lifting, executing high-speed digital signal processing, demodulation, and filtering..

[Audio] To make the system interactive, the FPGA communicates with a Touch Display, allowing an operator to monitor system metrics, view signals, and adjust configurations on the fly..

[Audio] Looking closely at the complete signal flow, we can trace the signal perfectly from the initial analog RF input, through automated protection, dual-path amplification, triple mixing stages, and finally into the digital processing domain..

RF_Input. Coupler. PD. MCU. DSA. 3.2GHz LPF. Pre Amp.

[Audio] This is the real hardware setup of our system..

[Audio] Now let's move on to the DSP Firmware on Zed board..