SECR2033 Computer Organization and Architecture

[Virtual Presenter] Lecture slides prepared for “Computer Organization and Architecture”, 9/e, by William Stallings, Chapter 1 “Introduction”..

This section describes the architecture of the x86 processor family and its host computer system from a programmer’s point of view. Assembly language is a great tool for learning how a computer works, and it requires you to have a working knowledge of computer hardware. The concepts in this section will help to understand the assembly language code that be written..

One. Basic Microcomputer Design. Irvine, K.R. (2011). Assembly Language for x86 Processors (6th Edition). New Jersey: Pearson Education Limited, p.30..

Irvine, K.R. (2011). Assembly Language for x86 Processors (6th Edition). New Jersey: Pearson Education Limited, p.30..

Irvine, K.R. (2011). Assembly Language for x86 Processors (6th Edition). New Jersey: Pearson Education Limited, p.31..

Instruction Execution Cycle. Irvine, K.R. (2011). Assembly Language for x86 Processors (6th Edition). New Jersey: Pearson Education Limited, p.31..

Reading From Memory. Irvine, K.R. (2011). Assembly Language for x86 Processors (6th Edition). New Jersey: Pearson Education Limited, p.33..

Multiple machine cycles are required when reading from memory, because it responds much more slower than the CPU..

How Program Run?. Assembling, Linking, and Running Programs.

Listing File. Use it to see how your program is compiled. Contains: source code addresses object code (machine language) segment names symbols (variables, procedures, and constants) Example: addSub.lst.

[image] Microsoft (R) Macro Assembler Version 9.00.30729.01 05/07/09 16:43:07 Add and Subtract TITLE Add and Subtract (AddSub. asm) Page I (AddSub. ) • This program adds and subtracts 32—bit integers. INCLUDE Irvine32. inc C . NOLIST C . LIST 00000000 00000000 00000000 00000005 0000000A OOOOOOOF 0000001B 05 2D 00010000 00040000 00020000 00000000 E . code main PROC add sub call eax, 1000 Oh eax, 4000 Oh eax, 2000 Oh DumpRegs EAX • EAX EAX = IOOOOh = 50000h = 30000h main ENDP END main Structures and Unions : Name Size Offset.

[image] Microsoft (R) Macro Assembler Version 9.00.30729.01 05/07/09 16:43:07 Add and Subtract TITLE Add and Subtract (AddSub. asm) Page I (AddSub. ) • This program adds and subtracts 32—bit integers. INCLUDE Irvine32. inc C . NOLIST C . LIST 00000000 00000000 00000000 00000005 0000000A OOOOOOOF 0000001B 05 2D 00010000 00040000 00020000 00000000 E . code main PROC add sub call eax, 1000 Oh eax, 4000 Oh eax, 2000 Oh DumpRegs EAX • EAX EAX = IOOOOh = 50000h = 30000h main ENDP END main Structures and Unions : Name Size Offset.

[image] Microsoft (R) Macro Assembler Version 9.00.30729.01 05/07/09 16:43:07 Add and Subtract TITLE Add and Subtract (AddSub. asm) Page I (AddSub. ) • This program adds and subtracts 32—bit integers. INCLUDE Irvine32. inc C . NOLIST C . LIST 00000000 00000000 00000000 00000005 0000000A OOOOOOOF 0000001B 05 2D 00010000 00040000 00020000 00000000 E . code main PROC add sub call eax, 1000 Oh eax, 4000 Oh eax, 2000 Oh DumpRegs EAX • EAX EAX = IOOOOh = 50000h = 30000h main ENDP END main Structures and Unions : Name Size Offset.

[image] Microsoft (R) Macro Assembler Version 9.00.30729.01 05/07/09 16:43:07 Add and Subtract TITLE Add and Subtract (AddSub. asm) Page I (AddSub. ) • This program adds and subtracts 32—bit integers. INCLUDE Irvine32. inc C . NOLIST C . LIST 00000000 00000000 00000000 00000005 0000000A OOOOOOOF 0000001B 05 2D 00010000 00040000 00020000 00000000 E . code main PROC add sub call eax, 1000 Oh eax, 4000 Oh eax, 2000 Oh DumpRegs EAX • EAX EAX = IOOOOh = 50000h = 30000h main ENDP END main Structures and Unions : Name Size Offset.

Map File. Information about each program segment: starting address ending address size segment type.

When a computer architecture is in the design phase, the instruction set format must be determined before many other decisions can be made. Selecting this format is often quite difficult because the instruction set must match the architecture. If the architecture is well designed, it could last for decades..

ISA Level defines the interface between the compilers (high level language) and the hardware. It is the language that both them understand..

Instruction Set Architectures (ISAs) are measured by several different factors, including: (1) the amount of space a program requires; (2) the complexity of the instruction set; (3) the length of the instructions; and (4) the total number of instructions..

The operation of the processor is determined by the instructions it executes, referred to as machine instructions or computer instructions. The collection of different instructions that the processor can execute is referred to as the processor’s instruction set. Each instruction must contain the information required by the processor for execution..

[Virtual Presenter] Next instruction reference is invisible Example: F10 in debugging, the IP (Instruction Pointer) show the instruction that not execute yet..

Opcode. Source Operand. Destination Operand. Source Operand with Immediate value.

Source and result operands (Destination) can be in one of four areas:.

0000 MOV AX,TOTAL 0001 MOV BX,AX 0002 ADD AX,2 0003 TARGET 0004 CALL READINT 0005 MOV VAL,EAX 0006 ADD EBX,VAL 0007 JMP TARGET.

Each instruction is represented by a sequence of bits that divided into fields, corresponding to the constituent elements of the instruction..

Thus, it has become common practice to use a symbolic representation of machine instructions. Opcodes are represented by abbreviations, called mnemonics, that indicate the operation..

During instruction execution: an instruction is read into an Instruction Register (IR) in the processor. The processor must be able to extract the data from the various instruction fields to perform the required operation..

Consider a high-level language instruction that could be expressed in a language such as C. Example:.

[Virtual Presenter] Intel machine code:  Opcode  address.

William Stallings (2013). Computer Organization and Architecture: Designing for Performance (9th Edition). United States: Pearson Education Limited, p.431..

Table 10.8 x86 Operation IYpes (with Examples of Typical Operations) Instruction Description.

Table 10.8 x86 Operation IYpes (with Examples of IYpical Operations) Instruction MOV PUSH PUSHA MOVSX LEA XLAT IN, OCT Description Data Movement Move operand, between registers or between register and memory. Push operand onto stack. Push all registers on stack. Move byte, word, dword, sign extended. Moves a byte to a word or a word to a doubleword with twos-complement sign extension. Load effective address. Loads the offset of the source operand, rather than its value to the destination operand. Table lookup translation. Replaces a byte in AL with a byte from a user-coded translation table. When XLAT is executed, AL should have an unsigned index to the table. XLAT changes the contents of AL from the table index to the table entry. Input, output operand from 1/0 space..

Table 10.8 x86 Operation IYpes (with Examples of Typical Operations) Instruction Description.

One of the traditional ways in describing processor architecture is using the number of addresses contained in each instruction ..

(c) One-address instructions. Instruction LOAD D MPY ADD c STOR LOAD A SUB DIV STOR Comment AC e D AC e AC X E AC e AC + C Y AC Y AC.

3 addresses: Operand 1, Operand 2, Result (Destination). May be a forth address - next instruction (usually implicit, obtained from PC (Program Counter)). Example below: T = temporary location used to store intermediate results. Not common in use. Needs very long words to hold everything..

2 addresses: Operand, Result (Destination). Reduces length of instruction and space requirements. Requires some extra works: Temporary storage to hold some results. Done to avoid altering the operand value..

1 address Implicit second address. Usually use a CPU register (accumulator) Supplies 1 operand and store result. One memory address used for other operand. Common on early machines..

0 (zero) address All addresses implicit. Usually use a stack (a push down stack in CPU). There are two Opcodes with one operand: PUSH op, POP op..

Stack machine: Java Virtual Machine. Call stack of a program, also known as a function stack, execution stack, control stack, or simply the stack. Application: Reverse Polish Notation (RPN), Depth-First-Search (DFS).

a b. a b. c. a b. d e. c. Expression tree. b c. a.

a b. c. Expression tree:. Left child of root “+”.

Expression tree:. (b) Postfix notation: Left-Right-Parent order.

Precedence of multiplication is higher than addition, we need parenthesis to guarantee execution order. However in the early 1950s, the Polish logician Jan Lukasiewicz observed that parentheses are not necessary in postfix notation, called RPN (Reverse Polish Notation). The Reverse Polish scheme was proposed by F.L. Bauer and E.W. Dijkstra in the early 1960s to reduce computer memory access and utilize the stack to evaluate expressions ..

Reverse Polish Notation (RPN)  Postfix order. Example:.

+ 1 5 8 4 1. 6 8 4 1. 6 8 3. Reverse Polish Notation (RPN)  Postfix order [1].

Scanned from left to right until an operator is found, then the last two operands must be retrieved and combined. Order of operands satisfy LIFO, so we can use stack to store operands and then evaluate RPN expression..

Switch (token ) Pop the top two values from the stack (if the stack does not contain two items, an error due to malformed RPN expression has occurred) Apply the operator to these two values. Push the resulting value back onto the stack. Push onto the stack Initialize an empty stack of operands get next token in RPN expression Only one value is on the stack YES end of infix expression NO + , - , * , / operand terminate.

1 push. 5 push 1. pop. 6 push. Example:. Evaluate RPN expression [2].

push 8. 6 push 8 4. push 6 8 4 1. pop 6 8. Example:.

pop 6. 6 push 5. Example:. Evaluate RPN expression [2].