Project : Reduction of VDD3_ACC_DIG Failure Rate DMAIC - Story Board

Project : Reduction of VDD3_ACC_DIG Failure Rate DMAIC - Story Board.

[Audio] This phase entails precisely describing the problem or opportunity for improvement, establishing project objectives, and understanding customer requirements..

[Audio] Terminal Pins VDD3 and VDD3_DIG are two independent voltage regulators that are used to supply the digital and analog blocks with 3.3V.This refers to the voltage level present at the VDD3 pin and is crucial for proper trimming of the device. An external capacitor is required to ensure stability of each regulator.During final testing, the voltage regulators were trimmed to 3.3 Volts to supply voltage VDD3 pins while maintaining a constant voltage..

[Audio] Business Case On the year 2023 It demonstrates that the VDD3_ACC_DIG regularly ranks as one of the top failing parameter in 50424-Brocap, resulting in a 4.10% yield loss on the first pass test. Which result to 21,000 Euros revenue lost For the year 2024 The projected is volume for the whole year for 50424-Brocap device is 4,971,436 units This project aims to reduced the failure rate from 4.10% or 204k units to 2.0% or 99k units that will result to 12k euros savings . This initiative is both a strategic imperative for our company and a chance to strengthen our market position, as it aims to increase production output while enhancing overall final test yield..

[Audio] Bar graph shows the failure rate of all the lots that run on the year 2023 averaging 4.10% failure rate..

[Audio] Line chart shows that the monthly Final Test yield for 2023 does not met the target FTY for production on 50424-Brocap. Final Test Yield does not met due to the over rejection on VDD3_ACC_DIG__ averaging 95.5% on the year 2023.

Project Team. Control. Improve. Analyse. Measure.

[Audio] the measure phase involves establishing a baseline for the existing process, collecting data, validating the measurement equipment, and determining process capacity..

[Audio] Graph show normal distribution for the parameter VDD3_DIG failure rate. With P value > 0.05 we can say that the data comes from a normal distribution.

[Audio] This sample data from lot H90811.1 During first pass test, There's a clear indication that we have a setup related issue on site 2. During Retest, Now the data shows that VDD_ACC_DIG failures occur in all sites. It shows that the failing units are not recoverable upon retest.

[Audio] The measurements on parameter VDD3_ACC_DIG are identical throughout the First Pass Test and the Production auto retest, indicating that the units are not recoverable on retest..

[Audio] The Six Sigma Analyze Phase is the third step in the DMAIC process, which is used to solve problems and generate plans. In this phase, we will review the data collected during the Measure Phase and make sense of it by formulating hypotheses about what is causing the problem or opportunity..

[Audio] After brainstorming with the team, we uncover various potential root causes and hypotheses that have an impact on the failure rate..

[Audio] We Identify potential root causes to be X1: The defective tester resource and X2: Different LoadBoard revisions. We will evaluate both of these potential root causes using histograms and a two-sample t-test..

[Audio] Data shows that mean of the BAD OVI board is significantly different to GOOD OVI board with p =0.039. Next step is to determine what causes the OVI board to wear out..

[Audio] Data shows that mean of the BAD OVI board is significantly different to GOOD OVI board with p =0.039. Next step is to determine what causes the OVI board to wear out..

[Audio] Box plot demonstrates that the measurement for the parameter VDD3_DIG became substantially more stable after changing the OVI board. On this summary shows wide reading on site 2 and 4 After swapping of OVI resource the site with wide variation of measurements was also interchange from site 2 and 4 to site 1 and 3 Data shows that after changing suspected OVI resource. Data is now stable..

[Audio] Testing X.2 or Different Load Board revisions Data shows that the Load Board rev B and rev C is not significantly different Load Board revision is not significant..

[Audio] Data shows that the Load Board rev B and rev C is not significantly different using histogram.

[Audio] For X.1, the conclusion is that tester resources that wear out have substantial variation in terms of measurements when compared to GOOD tester resources. For X.2, tester resources that wear out have large variation in terms of measurements when compared to GOOD tester resources. Red X: OVI resource is causing fluctuations of measurements for VDD_ACC_DIG test parameter. Latter showed failure in patterns; swapping the slots of OVI boards causes failures to interchange and always comes in pairs, for example, at sites 1 and 3, or at sites 2 and 4, which those sites share OVI resources. The challenge now is to find the main culprit causing the OVI resource to show instability of measurements..

[Audio] The Improve phase is the fourth stage of the DMAIC methodology. During this phase, teams work to eliminate root causes and make improvements based on the data analysis conducted in previous phases..

[Audio] X1.1: TDEV's advise on test program debugging: avoid auto-ranging. X1.2: Look for potential causes of mistrimming onTest program Debug: Trimming procedure..

[Audio] PLAN DO CHECK ACT for test program modification on auto ranging.

[Audio] Gather all of the resources needed.. Project “Reduction of VDD3_ACC_DIG Failure Rate“.

[Audio] Test program debug activity done by TDEV Sir Guido: At routine VDD3DIG_Pretrimming Change the current range first before forcing the maxload current - According to TDEV's recommendation, this prevents the force current and current range from being switched at the same time. Get back to 0 mA first before changing range As stated by TDEV, doing so will prevent "Auto-ranging," which occurs when the user does not define the range himself..

[Audio] Change the current range first before forcing the maxload current - According to TDEV's recommendation, this prevents the force current and current range from being switched at the same time. Get back to 0 mA first before changing range.

[Audio] Generate TP MSA report and check the any distributions that can be affected by the changes. Seek consent from TDEV Diane for the TP change and the result of the TP MSA. There is no substantial change in the measurement since the alterations done are simply for proper declaration of current range and proper turning on/off of current force...

[Audio] For the result, The failure rate of VDD3_ACC_DIG shows no improvement following a TP modification of the auto-ranging..

[Audio] PLAN DO CHECK ACT for X.1.2 which is checking of trimming method sequence.

[Audio] On Wafer Sort, the exact same wafer sort Test program procedure on VDD3_DIG_OVI was applied on both pre trimming and post trimming, but the wafer sort TP does not have the same wide distribution on the VDD3_DIG parameter as the Final Test TP. Compare the test programs and look for any changes in procedure..

[Audio] I discovered in the procedure VDD3DIG_Pretrimming that in the wafer sort, the "GATE ON" syntax comes before the "Connect OVI" I also saw a statement on the routine Chip ID about why he opted to turn on the gate first before connecting to the OVI..

[Audio] Apply the same sequence on Final Test TP : "GATE ON" first before "Connect OVI" syntax Compare the OLD TP vs the Modified TP: The "VDD3_ACC_DIG_SOFTTR" of modified has significantly more steady readings, with no spikes that cause the units to be mistrimmed as compared to the OLD TP..

[Audio] Perform a scope shot on the VDD3_DIG_OVI pin to see if there is any difference between GATE ON first and CONNECT OVI first. There is no substantial difference or voltage spike on the VDD3_DIG_OVI pin for either sequence..

[Audio] Ask for the approval of Test Engineering is we can also apply this modification on Final Test and he agreed. Also according to Test Engineer the modification is safe and will not have high current over the relays, because we force just a small current and the current for parasitics is also small..

[Audio] Perform test program MSA to confirm that the distributions of all parameters are not impacted by the TP adjustment. There is no substantial change in the measurement.

[Audio] The sample STDF shown below were taken from lots that used the exact same setup and peripherals but had a different TP revision. Previous Test program shows wide distribution and sudden spikes on measurement that causes over rejection After TP revision the parameter VDD3_DIG has now much more stable reading and minimal spikes.

[Audio] Test program comparison on the failure rate of VDD3_DIG parameter Data from Q1 to Q2 of 2024 demonstrate that the desired failure rate was achieved following the test program modification K1..

[Audio] Test program revision comparison of failure rate of VDD3_DIG from the 1st half of year 2024 The Pareto of Test Program Comparison from the first half of 2024 shows that the parameter VDD3_ACC_DIG___ is the top failing parameter for the 50424-Brocap device. After modifying the TP on version K1, the failure rate drops from 3.48% to 0.71%..

[Audio] The Control Phase, the final step in the DMAIC approach, strives to put safeguards in place to ensure that the improvements recognized in earlier phases are sustained..

[Audio] The project's secondary metric or FTY target was met following the Test program modification during work week 26.

[Audio] The target final test yield and failure rate have been met. Also, no more Nogo reporting was recorded due to the overrejection of VDD3_ACC_DIG..

[Audio] Cost Savings: Failure rate Improvement Total of 20,628.28 EUR cost savings per year.

[Audio] Cost Savings: Down Time reduction for TPE is equals to € 19,220.40 per year Cost Savings: Down Time reduction for ME (CAL/DIAG, SWAPPING and REPLACEMENT of OVI BOARD is equals to € 760.00 per year.

[Audio] TOTAL COST SAVINGS of € 40,608.68 per year.

[Audio] Failure rate was now drop from the average 4.10% to 0.71% and lower than the target of 2% The target cost reductions for the scrapped units were 12,778.72 euros, and the actual cost savings were higher, at 20,628.28 euros..

[Audio] The reduction of VDD3_ACC_DIG failure rate is successful, with an actual failure rate of 0.71%. The parameter VDD3_ACC_DIG was eliminated as the leading cause of failure rate. A cost savings of € 40,608.68 per year..

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