10.2 I/O Fundamentals

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10.2 I/O Fundamentals.

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Introduction. We can divide I/O into three areas. The strategy by which data is moved The interface circuit that actually moves the data The input/output devices themselves that convert data into a form that can be used by an external system or that take data from the outside world and convert it into a form that can be processed digitally..

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Example. Computer The program MOVE. B data, DO MOVE. B DO, outpu Parallel to serial converter Display Serial data Transmission path CZA Display controller Serial to parallel converter.

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Example. Computer The program MOVE. B data, DO MOVE. B DO, outpu Parallel to serial converter Display Serial data Transmission path CZA Display controller Serial to parallel converter.

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CPU, Interface and Device. ata us CPU Part of the com uter Perip ral interf ce chip CPU side Peripheral side Peripheral device Peripheral bus An external device.

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Example. Writing a block of data to a disk drive Impractical to use programmed data transfers for disk I/O (too slow). Direct Memory Access (DMA) is used The CPU tells the DMA Controller (DMAC)to move a block of data and the DMAC gets on with the task This allows the CPU to continue its main function of information processing..

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Programmed I/O. Takes place when an instruction in the program performs the data transfer Ex. MOVE . B Keyboard, DO to read a byte of data from the keyboard and puts it in DO. Some microprocessors have special instructions that are used only for I/O Ex. OUT 123 to place the contents of a data register on the data bus. Each of the I/O ports in such a system monitors the address lines. When an I/O interface sees its own address together with a read-port or a write-port signal, the interface executes an I/O data transfer..

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I/O addressing modes. Memory mapped I/O Ex. MOVE . B Keyboard, DO Ex. MOVE . B DO, Screen Isolated I/O Ex. OUT 123 Ex. IN 2000.

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Memory-mapped I/O. Microprocessors without special I/O instruction must use memory-mapped I/O there is a single address space for memory locations and I/O devices The processor treats interface ports as an extension to memory (I/O ports look exactly like normal memory locations) and uses the same machine instructions to access both memory and I/O devices . Ex. with 10 address lines, a combined total of 1024 memory locations and I/O addresses can be supported, in any combination..

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Memory-mapped I/O. Address bus Data bus Data Address Data Address Memory CPU Data Address Output port Output lines To eri heral 000000 000400 Program 0007FF 002000 Data 0020FF 008000 Output port 008003.

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Isolated I/O. Supports separate address spaces for memory and I/O devices The full range of addresses is available for both. With 10 address lines, the system may now support both 1024 memory locations and 1024 I/O addresses. Regular instructions like MOV reference RAM. The special instructions such as IN, Out access a separate I/O address space The bus is equipped with M/IO line. The line specifies whether the address refers to a memory location or an I/O device..

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Isolated I/O. Data Data bus Data Address CPU Address Data Address Memory Output port Output lines To peripheral.

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* FOR i Move END?OR 1 to 128 data from to output_port PORT EQU COUNT EQU ORG •k MOVE LEA LEA .sgg TBNE ORG TABLE DS. B $008000 128 5000400 *COUNT , Dl TABLE , AO PORT, A1 $0020C0 128 Location Of memory—mapped port Size Of block to be output Origin of program [Dll [AOI 128 TABLE Portl Set up loop counter AO points to the table A1 points to the port - 'dat•a.i bé@utput:- OGEpUt:• the • 'dat-a• .8 RéÉ,eaf' Origin for data area Reserve 128 bytes for the table Of data €10. ' Table 10.1 A hypothetical example of a programmed output transfer..

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* FOR i Move END?OR 1 to 128 data from to output_port PORT EQU COUNT EQU ORG •k MOVE LEA LEA .sgg TBNE ORG TABLE DS. B $008000 128 5000400 *COUNT , Dl TABLE , AO PORT, A1 $0020C0 128 Location Of memory—mapped port Size Of block to be output Origin of program [Dll [AOI 128 TABLE Portl Set up loop counter AO points to the table A1 points to the port - 'dat•a.i bé@utput:- OGEpUt:• the • 'dat-a• .8 RéÉ,eaf' Origin for data area Reserve 128 bytes for the table Of data €10. ' Table 10.1 A hypothetical example of a programmed output transfer..

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. The program is unsuited to almost all real situations. Most peripherals connected to an output port are slow devices Sending data to them at this rate  all the data being lost. Solution: ask the peripheral if it's ready to receive data, and not sending data to it until it is ready to receive it. (S oftware handshaking procedure) A status byte is associated with the port..

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8000 location of the port to which data is sent 8002 location of the status byte. bit 0 of the status byte is a 1 if the port is ready for data and a 0 if it is busy. The following program outputs data at a rate determined by the peripheral..

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FOR i - 1 TO 128 REPEAT Read UNTIL Pozt_not busy Move data from Tablei to output_port 1 2. 3. 4. 5. 9. 10. 11. 12. 13. 14. 15. 17. 18. ENDFOR PORTOATA PORTSTÄT COUNT LOOP WAIT TABLE EQU EQU EQU ORG MOVE LEA LEA LEA MOVE . B MOVE . B AND. B MOVä . B BNE ORG DS. B 3008000 $008002 128 $000400 COUNT , Dl TABLE, AO PORTOATA , A1 (A2) ,D2 WAIT DO, (A1) LOOP $002COO 128 Locat ion of memory—mapped port Location of port's Status byte Size of block to be Output Origin of program Set up character counter in 01 AO points table in memory AJ points to data port A2 points to port status byte Get a byte from the table REPEAT Read status Mask all but Of status Until port ready Store data in peripheral Decrement loop counter Repeat until = O Start of data area Reserve 12B bytes of data Table 10.2 Using the polling loop to control the flow of data..

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FOR i - 1 TO 128 REPEAT Read UNTIL Pozt_not busy Move data from Tablei to output_port 1 2. 3. 4. 5. 9. 10. 11. 12. 13. 14. 15. 17. 18. ENDFOR PORTOATA PORTSTÄT COUNT LOOP WAIT TABLE EQU EQU EQU ORG MOVE LEA LEA LEA MOVE . B MOVE . B AND. B MOVä . B BNE ORG DS. B 3008000 $008002 128 $000400 COUNT , Dl TABLE, AO PORTOATA , A1 (A2) ,D2 WAIT DO, (A1) LOOP $002COO 128 Locat ion of memory—mapped port Location of port's Status byte Size of block to be Output Origin of program Set up character counter in 01 AO points table in memory AJ points to data port A2 points to port status byte Get a byte from the table REPEAT Read status Mask all but Of status Until port ready Store data in peripheral Decrement loop counter Repeat until = O Start of data area Reserve 12B bytes of data Table 10.2 Using the polling loop to control the flow of data..

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Interrupt-driven I/O. Polling is grossly inefficient because so much of the computer's time is wasted waiting for the port to become free. A powerful computer working in a multiprogramming environment can attend to another task program during the time the I/O port is busy. A better I/O strategy is to ignore the peripheral until it is ready for a data transfer and then let the peripheral ask the CPU for attention. Such a strategy is called interrupt-driven I/O ..

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Interrupt-driven I/O. Address bus Data bus CPU Memory IRQ Interrupt request to CPU Port Data register Status register Interrupt registers are read by the CPU to determine the peripheral's status Informs CPU that the peripheral wants attention IVR I want attention.

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Interrupt-driven I/O. A computer executes instructions sequentially unless a jump or a branch is made. Interrupt –also- forces the CPU to modify its sequence of actions. This event may be a signal from a peripheral (i.e. a hardware interrupt) or an internally generated call to the operating system (i.e. a software interrupt). The term exception describes both hardware and software interrupts. The interrupt request input, IRQ, may or may not be granted..

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Interrupt-driven I/O. When the CPU detects that its IRQ input has been asserted, the following sequence of events takes place. The CPU finishes its current instruction The contents of the program counter and the processor status word are pushed onto the stack. Further interrupts are disabled to avoid an interrupt being interrupted The CPU deals with the interrupt by executing a program called an interrupt handler or Interrupt Service Routine ISR. The CPU executes a return from interrupt instruction at the end of the interrupt handler. Executing this instruction pulls the PC and processor status word off the stack and execution then continues normally—as if the interrupt had never happened..

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Interrupt-driven I/O. Normal processing Interrupt Stack processor status and return address Restore PC and processor status Interrupt handling Save working registers Interrupt handling routine Restore working registers Stack before interrupt Stack SP TOS Stack after interrupt Stack Return Status Old TOS.

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Pick up pointer to next free entry in the table (buffer) Read a byte from the table and transmit it to the interface Move the pointer to the next entry in the table and save the pointer Return from in memory interrupt $008000 OUTPUT EQU $0C04CO ORG LEA POINTER, AO MOVE . B (Ad) % OUTPUT MOVE. L AO,m1NTER RTE $002000 ORG BUFFER DS .B 1024 POINTER DS.L 1 Table 10.3 A simple interrupt handler. Location of memory-mapped output port Start of the program fragment Load AO with the pointer to the buffer Read character from buffer and output Save the updated pointer Return from interrupt Data origin Reserve 1024 bytes for the table Reserve a longword for the pointer.